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hm62w16255hci series wide temperature range version 4m high speed sram (256-kword 16-bit) ade-203-1263 a (z) rev. 1 .0 nov . 1 , 2001 description the hm62w16255hci is a 4-mbit high speed static ram organized 256-kword 16-bit. it has realized high speed access time by employing cmos process (6-transistor memory cell) and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. the hm62w16255hci is packaged in 400-mil 44-pin soj and 400-mil 44-pin plastic tsopii for high density surface mounting. features single 3.3 v supply: 3.3 v 0.3 v access time: 12 ns (max) completely static memory ? no clock or timing strobe required equal access and cycle times directly ttl compatible ? all inputs and outputs operating current: 130 ma (max) ttl standby current: 40 ma (max) cmos standby current: 5 ma (max) center v cc and v ss type pinout temperature range: ?40 to +85 c
hm62w16255hci series rev.1, nov. 2001, page 2 of 17 ordering information type no. access time device marking package hm62w16255hcjpi-12 12 ns HM62W16255CJPI12 400-mil 44-pin plastic soj (cp-44d) hm62w16255hctti-12 12 ns hm62w16255ctti12 400-mil 44-pin plastic tsopii (ttp-44de)
hm62w16255hci series rev.1, nov. 2001, page 3 of 17 pin arrangement pin description pin name function a0 to a17 address input i/o1 to i/o16 data input/output cs chip select oe output enable we write enable ub upper byte select lb lower byte select v cc power supply v ss ground nc no connection
hm62w16255hci series rev.1, nov. 2001, page 4 of 17 block diagram
hm62w16255hci series rev.1, nov. 2001, page 5 of 17 operation table cs cs oe oe we we lb lb ub ub mode v cc current i/o1?i/o8 i/o9?i/o16 ref. cycle h standby i sb , i sb1 high-z high-z ? l h h output disable i cc high-z high-z ? l l h l l read i cc output output read cycle l l h l h lower byte read i cc output high-z read cycle l l h h l upper byte read i cc high-z output read cycle l l h h h ? i cc high-z high-z ? l l l l write i cc input input write cycle l l l h lower byte write i cc input high-z write cycle l l h l upper byte write i cc high-z input write cycle l l h h ? i cc high-z high-z ? note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ?0.5 to +4.6 v voltage on any pin relative to v ss v t ?0.5* 1 to v cc + 0.5* 2 v power dissipation p t 1.0 w operating temperature topr ?40 to +85 c storage temperature tstg ?55 to +125 c storage temperature under bias tbias ?40 to +85 c notes: 1. v t (min) = ?2.0 v for pulse width (under shoot) 6 ns 2. v t (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns
hm62w16255hci series rev.1, nov. 2001, page 6 of 17 recommended dc operating conditions (ta = ?40 to +85c) parameter symbol min typ max unit supply voltage v cc * 3 3.0 3.3 3.6 v v ss * 4 0 0 0 v input voltage v ih 2.0 ? v cc + 0.5* 2 v v il ?0.5* 1 ? 0.8 v notes: 1. v il (min) = ?2.0 v for pulse width (under shoot) 6 ns 2. v ih (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns 3. the supply voltage with all v cc pins must be on the same level. 4. the supply voltage with all v ss pins must be on the same level. dc characteristics (ta = ?40 to +85c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol min typ* 1 max unit test conditions input leakage current |i li | ? ? 2 a vin = v ss to v cc output leakage current |i lo | ? ? 2 a vin = v ss to v cc operating power supply current i cc ? ? 130 ma min cycle cs = v il , iout = 0 ma other inputs = v ih /v il standby power supply current i sb ? ? 40 ma min cycle, cs = v ih , other inputs = v ih /v il i sb1 ? 2.5 5 ma f = 0 mhz v cc 3 cs 3 v cc ? 0.2 v, (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc ? 0.2 v output voltage v ol ? ? 0.4 v i ol = 8 ma v oh 2.4 ? ? v i oh = ?4 ma notes: 1. typical values are at v cc = 3.3 v, ta = +25c and not guaranteed.
hm62w16255hci series rev.1, nov. 2001, page 7 of 17 capacitance (ta = +25c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin ? ? 6 pf vin = 0 v input/output capacitance* 1 c i/o ? ? 8 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62w16255hci series rev.1, nov. 2001, page 8 of 17 ac characteristics (ta = ?40 to +85c, v cc = 3.3 v 0.3 v, unless otherwise noted.) test conditions input pulse levels: 3.0 v/0.0 v input rise and fall time: 3 ns input and output timing reference levels: 1.5 v output load: see figures (including scope and jig) read cycle hm62w16255hci -12 parameter symbol min max unit notes read cycle time t rc 12 ? ns address access time t aa ? 12 ns chip select access time t acs ? 12 ns output enable to output valid t oe ? 6 ns byte select to output valid t lb , t ub ? 6 ns output hold from address change t oh 3 ? ns chip select to output in low-z t clz 3 ? ns 1 output enable to output in low-z t olz 0 ? ns 1 byte select to output in low-z t lblz , t ublz 0 ? ns 1 chip deselect to output in high-z t chz ? 6 ns 1 output disable to output in high-z t ohz ? 6 ns 1 byte deselect to output in high-z t lbhz , t ubhz ? 6 ns 1
hm62w16255hci series rev.1, nov. 2001, page 9 of 17 write cycle hm62w16255hci -12 parameter symbol min max unit notes write cycle time t wc 12 ? ns address valid to end of write t aw 8 ? ns chip select to end of write t cw 8 ? ns 8 write pulse width t wp 8 ? ns 7 byte select to end of write t lbw , t ubw 8 ? ns 9, 10 address setup time t as 0 ? ns 5 write recovery time t wr 0 ? ns 6 data to write time overlap t dw 6 ? ns data hold from write time t dh 0 ? ns write disable to output in low-z t ow 3 ? ns 1 output disable to output in high-z t ohz ? 6 ns 1 write enable to output in high-z t whz ? 6 ns 1 notes: 1. transition is measured 200 mv from steady voltage with output l oad (b). this parameter is sampled and not 100% tested. 2. if the cs or lb or ub low transition occurs simultaneously with the we low transition or after the we transition, output remains a high impedance state. 3. we and/or cs must be high during address transition time. 4. if cs , oe , lb and ub are low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 5. t as is measured from the latest address transition to the latest of cs , we , lb or ub going low. 6. t wr is measured from the earliest of cs , we , lb or ub going high to the first address transition. 7. a write occurs during the overlap of low cs , low we and low lb or low ub . 8. t cw is measured from the later of cs going low to the end of write. 9. t lbw is measured from the later of lb going low to the end of write. 10. t ubw is measured from the later of ub going low to the end of write.
hm62w16255hci series rev.1, nov. 2001, page 10 of 17 timing waveforms read timing waveform (1) ( we = v ih )
hm62w16255hci series rev.1, nov. 2001, page 11 of 17 read timing waveform (2) ( we we = v ih , lb lb = v il , ub ub , = v il )
hm62w16255hci series rev.1, nov. 2001, page 12 of 17 write timing waveform (1) ( lb , ub controlled)
hm62w16255hci series rev.1, nov. 2001, page 13 of 17 write timing waveform (2) ( we controlled)
hm62w16255hci series rev.1, nov. 2001, page 14 of 17 write timing waveform (3) ( cs controlled)
hm62w16255hci series rev.1, nov. 2001, page 15 of 17 package dimensions hm62w16255hcjpi series (cp-44d)
hm62w16255hci series rev.1, nov. 2001, page 16 of 17 hm62w16255hctti series (ttp-44de)
hm62w16255hci series rev.1, nov. 2001, page 17 of 17 disclaimer 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. produ cts and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of hi gh quality and reliability. however, contact hitachi?s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi part icularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. c ontact hitachi?s sales office for any questions regarding this document or hitachi semiconductor products. sales offices title: (adaddsem010416.eps) creator: adobe illustrator(tm) 5.5 preview: this eps picture was not saved with a preview included in it. comment: this eps picture will print to a postscript printer, but not to other types of printers.

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